The subject matter disclosed herein relates to solutions for thinning semiconductor-on-insulator (SOI) layers in a semiconductor device. Specifically, the subject matter disclosed herein relates to solutions for forming extremely-thin semiconductor-on-insulator (ETSOI) wafers including at least one recess.
Complementary metal-oxide semiconductor (CMOS) devices built on an extremely (see also, extra) thin semiconductor-on-insulator (SOI) substrate have been one of the viable options for continued scaling of CMOS technology to the 22 nm node and beyond. Device characteristics such as threshold voltage (Vt) of an extra-thin SOI (ETSOI) device are partially determined by the thickness of the ETSOI. Consequently, controlling SOI thickness within a wafer helps prevent undesirable Vt variation. For the 22 nm node and beyond, the SOI thickness requirement may be about 10 nm or thinner. Currently, SOI wafers are generated having thicknesses that are significantly thicker than 60 nm, and are then thinned to the ETSOI level. One current wafer thinning technique includes a series of oxidation and etching steps, performed successively, over the course of one week to ten days. This technique, like others not discussed for the purposes of clarity, can be costly and time-intensive.